m68k: mvme147,mvme16x: Don't wipe PCC timer config bits
Don't clear the timer 1 configuration bits when clearing the interrupt flag
and counter overflow. As Michael reported, "This results in no timer
interrupts being delivered after the first. Initialization then hangs
in calibrate_delay as the jiffies counter is not updated."
On mvme16x, enable the timer after requesting the irq, consistent with
mvme147.
No advisories yet.
Solution
No solution given by the vendor.
Workaround
No workaround given by the vendor.
Thu, 09 Jan 2025 20:15:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| First Time appeared |
Linux
Linux linux Kernel |
|
| Weaknesses | NVD-CWE-noinfo | |
| CPEs | cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:* | |
| Vendors & Products |
Linux
Linux linux Kernel |
|
| Metrics |
cvssV3_1
|
cvssV3_1
|
Mon, 04 Nov 2024 13:15:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| Metrics |
ssvc
|
Projects
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Status: PUBLISHED
Assigner: Linux
Published:
Updated: 2025-05-04T07:02:22.493Z
Reserved: 2024-02-27T18:42:55.954Z
Link: CVE-2021-47016
Updated: 2024-08-04T05:24:39.559Z
Status : Analyzed
Published: 2024-02-29T23:15:07.307
Modified: 2025-01-09T19:52:27.117
Link: CVE-2021-47016
OpenCVE Enrichment
No data.